RISC-V¶

April 5, 2026
in FPGA, RISC-V, DOOM, Tang Nano 20K
4 min read

Building a custom SoC to run DOOM

This page will describe my experience building a custom RISC-V CPU for the sole purpose of running DOOM on a small FPGA (the Gowin Tang Nano 20K).
I will be creating a custom instruction set (RV32doom?) that augments the base RV32IM with instructions useful for running DOOM at full resolution and framerate on this FPGA. I will also be implementing all of the Uncore components necessary for the CPU to function.

December 10, 2025
in RISC-V, ASIC, FPGA, Synthesis, Physical Layout
5 min read

tiny-riscv: A small RV32E CPU

tiny-riscv is (true to its uninspired name) an attempt to build the smallest RISC-V core possible while maintaing roughly one Instruction per Cycle. It achieves this by supporting the base RV32E instruction set with a simple two stage pipeline. The implementation targets the FreePDK45nm standard cell library.

core_diagram A very simplified diagram of the core pipeline