• December 10, 2025
• in RISC-V, ASIC, FPGA, Synthesis, Physical Layout
• 5 min read

tiny-riscv: A small RV32E CPU

tiny-riscv is (true to its uninspired name) an attempt to build the smallest RISC-V core possible while maintaing roughly one Instruction per Cycle. It achieves this by supporting the base RV32E instruction set with a simple two stage pipeline. The implementation targets the FreePDK45nm standard cell library.

A very simplified diagram of the core pipeline