SystemVerilog¶

March 16, 2026
in ADS-B, SDR, DSP, FPGA, CPLD
6 min read

Decoding ADS-B on an FPGA

This project implements a complete, hardware-based ADS-B receiver pipeline by interfacing a HackRF One directly with a Gowin FPGA.

demo A demo of the working decoder receiving messages from a passing plane

December 10, 2025
in RISC-V, ASIC, FPGA, Synthesis, Physical Layout
5 min read

tiny-riscv is (true to its uninspired name) an attempt to build the smallest RISC-V core possible while maintaing roughly one Instruction per Cycle. It achieves this by supporting the base RV32E instruction set with a simple two stage pipeline. The implementation targets the FreePDK45nm standard cell library.

core_diagram A very simplified diagram of the core pipeline

Decoding ADS-B on an FPGA

tiny-riscv: A small RV32E CPU